1. Field of the Invention
The present invention generally relates to solid state imagers and, more particularly, is directed to a solid state imager in which a dynamic range of a final bit in a horizontal transfer unit is improved.
2. Description of the Prior Art
FIG. 1 shows a structure of a solid state imager of, for example, an interline transfer type as an example of a conventional solid state imager.
Referring to FIG. 1, it will be seen that an imager unit 3 is formed of a plurality of sensitive units 1 arrayed in the unit of pixels in the horizontal and vertical directions for storing electric charges corresponding to an amount of an incident light and a vertical transfer unit composed of a plurality of vertical shift registers 2 for transferring electric charges instantly read out from these sensitive units 1 during one portion of a vertical blanking period at every vertical column. In the imager unit 3, each of the sensitive units 1 is formed of, for example, a photodiode and each of the vertical shift registers 2 is formed of a charge coupled device (CCD). An electric charge read out to the vertical shift register 2 is sequentially transferred to a horizontal shift register (horizontal transfer unit) 4 at its every portion corresponding to one line by driving the vertical shift register 2 by 4-phase clock voltages .phi..sub.V1 to .phi..sub.V4 during one portion of the horizontal blanking period. The horizontal shift register 4 is formed of a CCD. An electric charge of one line is sequentially transferred to the horizontal direction by driving the horizontal shift register 4 by 2-phase clock voltages .phi..sub.H1 and .phi..sub.H2. An output circuit unit 5 formed of a floating diffusion amplifier (FDA) or the like is provided at the final stage of the horizontal shift register 4. The output circuit unit 5 converts electric charges, which are photo-electrically-converted by the sensing unit 1 and vertically and horizontally transferred, into voltages and then derives the same as a signal output voltage OUT.
In the CCD solid state imager thus arranged, as is clear from FIG. 2 which shows a sectional structure of the horizontal shift register 4, the horizontal shift register 4 is constructed as follows: As shown in FIG. 2, a plurality of transfer electrodes 8.sub.1, 8.sub.2, . . . , 8.sub.n, each formed of electrode pair of bilayer structure are arrayed, for example, on a silicon semiconductor substrate 6 via an insulating film 7 in the transfer direction and one electrode of each electrode pair and the other electrode thereof are coupled each other as a transfer unit TR and a storage unit ST, thereby the horizontal shift register 4 being constructed as charge transfer units (transfer electrodes) of a plurality of bits. Then, transfer electrode groups (8.sub.1, 8.sub.3, . . . ) of every other bit involving the transfer electrode 8.sub.1 of the final bit are commonly coupled and other transfer electrode groups (8.sub.2, 8.sub.4, . . . ) of every other bit are similarly commonly coupled and the clock voltages .phi..sub.H1 and .phi..sub.H2 of the same waveform shown in FIG. 3 are applied to these two sets of transfer electrode groups, thereby the horizontal shift register 4 being driven in a two-phase fashion. A gate electrode 9 is formed at the rear stage of the transfer electrode 8.sub.1 of the final bit on the substrate 6 through the insulating layer 7 to thereby construct a horizontal output gate unit HOG.
In the above-mentioned horizontal shift register 4, a dynamic range of the electric charge transfer unit (transfer electrode 8.sub.1) of the final bit (final stage) is determined by a difference between a potential of the horizontal output gate unit HOG and a potential of the storage unit ST in the transfer electrode 8.sub.1 of the final bit unlike the electric charge transfer unit of other bit. As a consequence, before electric charges are transferred to the output circuit unit 5 (see FIG. 1), when electric charges are stored in the transfer electrode 8.sub.1 of the final bit, electric charges are stored from the transfer electrode 8.sub.2 to the transfer electrode 8.sub.1 and simultaneously electric charges are transferred from the transfer electrode 8.sub.1 through the horizontal output gate unit HOG to the floating diffusion portion (FD) which is the output circuit unit 5 from a timing relation of the clock voltages .phi..sub.H1 and .phi..sub.H2 as shown in a potential diagram of FIG. 4. That is, electric charges are overflowed at the horizontal output gate unit HOG and flowed to the floating diffusion portion FD, which phenomenon will hereinafter be referred to as an electric charge flooding phenomenon for simplicity. If this electric charge flooding phenomenon occurs, there is then the problem that the dynamic range of the final bit becomes smaller than the dynamic range obtained from a principle standpoint.
In order to increase the dynamic range of the final bit, the following methods are proposed:
(1) To increase the amplitudes of the clock voltages .phi..sub.H1 and .phi..sub.H2 for horizontal transfer driving; and
(2) To apply other clock voltage only to the final bit. The method (1) becomes opposite to the recent trend such that the clock voltage is lowered more and more. Further, the method (2) causes the number of terminals to be increased and also causes a clock voltage generator to become complicated in arrangement.
On the other hand, there is a large possibility that the above-mentioned so-called electric charge flooding phenomenon occurs when the amplitude of the clock voltage applied to the transfer electrode 8.sub.1 of the final bit is selected to be the same as that of the clock voltage applied to the other transfer electrode. At that time, the electric charge flooding phenomenon is associated with the phase of the leading edge of the clock voltage .phi..sub.H1 and the phase of the trailing edge of the clock voltage .phi..sub.H2 and the assignee of the present application has confirmed that the above-mentioned electric charge flooding phenomenon occurred when the cross point P therebetween was at low level.